The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also correspond to embodiments of the claimed subject matter.
Real Time Instruction Tracing (RTIT) is a debug feature that logs what instructions are being executed by a processor. RTIT explains what instructions were executed by a processor by generating packets with specifying target information of indirect jumps. Because the near RET (RETurn) instructions are usually the most frequent indirect jump, much of the trace output and bandwidth is consumed by packets generated by RET instructions. This bandwidth contributes to computational overhead which does not directly solve a problem or task handled by the processor. Conventional RTIT mechanisms provide no means by which such wasteful overhead may be reduced.
The present state of the art may therefore benefit from systems and methods for implementing Real Time Instruction Tracing (RTIT) compression of RET (Return) instructions as described herein.